1. Field of the Invention
The present invention relates generally to capacitors formed within integrated circuits. More particularly, the present invention relates to stacked container capacitors formed within integrated circuits.
2. Description of the Related Art
Well known in the art of integrated circuit memory chip design and fabrication is the single memory cell which is comprised of an access transistor which serves as a switching element through which an associated storage capacitor may be charged and discharged. The single memory cell provides an element within advanced digital integrated circuits through which large quantities of data may be stored, manipulated and retrieved.
As integrated circuit technology has advanced, and integrated circuit device dimensions have decreased, it has become increasingly important to efficiently form within advanced integrated circuits storage capacitors which comply with the conflicting requirements of high charge storage capacity and decreased physical dimensions. Storage capacitors which possess these two criteria allow continued scaling of integrated circuit device memory cells and efficient use of semiconductor substrate surface area while simultaneously providing sufficient charge storage capacity to assure integrity of data storage and retrieval without data losses due to adventitious circuit noise and related charge generation phenomena.
Methods through which there may be formed integrated circuit device memory cells, and the storage capacitors associated with those cells, are well known in the art. Most commonly, the storage capacitors within integrated circuit memory cells are formed within trenches or other apertures formed within the semiconductor substrates adjoining the transistors through which those storage capacitors are accessed. Storage capacitors formed in this location are referred to as trench storage capacitors.
Less common in the art are analogous storage capacitors which are formed within or through a dielectric layer directly above or upon the source/drain electrode of a field effect transistor which accesses that storage capacitor. When formed in this location, the storage capacitor is commonly referred to as a stacked container capacitor. Stacked container capacitors provide particularly space efficient integrated circuit memory cells. It is towards forming stacked container capacitors with fully planarized surfaces and readily accessible electrodes that the present invention is directed. Stacked container capacitors formed with those properties are most likely to be readily fabricated into advanced integrated circuits with maximum process flexibility.
The art teaches many improvements and variations upon methods for forming trench storage capacitors for use within integrated circuit device memory cells. For example, Shibata, in U.S. Pat. No. 4,577,395 teaches a multiple masking and self-aligning method for forming a trench storage capacitor which has limited susceptibility to electrical punch-through to an adjoining trench storage capacitor. In addition, Kenney, in U.S. Pat. No. 4,833,094 teaches a method for forming a mandrel shaped trench storage capacitor which rises slightly above the surface of the semiconductor substrate within which it is formed. One of the vertical electrodes of the capacitor is connected to the source/drain electrode of the transistor through which the trench storage capacitor is accessed via a novel doped polysilicon bridge element.
Further, Lee, in U.S. Pat. No. 5,026,659 teaches a method for forming a trench storage capacitor having improved electrical integrity. The method incorporates a junction implant and an oxide spacer layer at the bottom of the trench into which is formed the trench storage capacitor. Still further, Ellul et al., in U.S. Pat. No. 5,275,974 teaches a maskless method for forming electrodes for a trench storage capacitor. The method employs a trench having two separate sections of different width.
Yet further, Anzai, in U.S. Pat. No. 5,292,679 discloses a non-etching method for forming trench storage capacitors. The method provides trenches which are formed through selective growth of an epitaxial layer using a silicon oxide mask. Finally, Chu et al., in U.S. Pat. No. 5,384,152 teach a method for forming trench storage capacitors of higher capacitance. The disclosed method employs roughened capacitor plate surfaces formed through providing lattice mis-matched crystal layers upon those surfaces.
Less common in the art are disclosures relating to stacked container capacitors. Dennison et al., in U.S. Pat. Nos. 5,162,248 and 5,270,241 disclose a method for forming a stacked container capacitor which protrudes above the surface of an insulating layer into which the stacked container capacitor is formed. Fabrication of the stacked container capacitor involves a planarizing process for filling the stacked container capacitor with a sacrificial oxide.
Desirable in the art are additional improvements to stacked container capacitors. Particularly desirable are improvements which provide stacked container capacitors having a fully planarized structure in their final states, and stacked container capacitors wherein electrodes are readily accessible for connection to other electrical circuit elements within the integrated circuits within which are formed those stacked container capacitors.